18
425112fd
LTC4251/LTC4251-1/
LTC4251-2
For more information www.linear.com/4251
APPLICATIONS INFORMATION
Analog Current Limit and Fast Current Limit
In Figure 13a, when SENSE exceeds V
ACL
, GATE is regulated
by the analog current limit amplifier loop. When SENSE
drops below V
ACL
, GATE is allowed to pull up. In Figure
13b, when a severe fault occurs, SENSE exceeds V
FCL
and GATE immediately pulls down until the analog current
amplifier can establish control. If TIMER reaches V
TMRH
,
GATE pulls low and latches off.
Resetting a Fault Latch
As shown in Figure 14, a latched fault is reset by either
pulling UV/OV below V
UVLO
or pulling TIMER below V
TMRL
.
An initial timing cycle is initiated if UV/OV is used for reset.
If TIMER is used for reset, the initial timing cycle is skipped.
Internal Soft-Start
An internal soft-start feature ramps the positive input of
the analog current limit amplifier during initial start-up.
The ramp duration is approximately 200祍. This feature
reduces load current dl/dt at start-up. As illustrated in
Figure?5, soft-start is initiated by a TIMER transition from
V
TMRH
to V
TMRL
or when UV/OV falls below the V
OVLO
threshold after an OV fault. After soft-start duration, load
current is limited by V
ACL
/R
S
.
Figure 9. Undervoltage Lockout Timing (All Waveforms are Referenced to V
EE
)
1
3
2
4 5 6
7 8 9
V
UV/0V
CLEARS V
UVHI
, CHECK TIMER < V
TMRL
, GATE < V
GATEL
AND SENSE < V
CB
.
V
UV/0V
DROPS BELOW V
UVLO
. TIMER, GATE, AND SENSE ARE PULLED TO V
EE
.
TIMER CLEARS V
TMRL
, CHECK GATE < V
GATEL
AND SENSE < V
CB
.
V
UVHI
V
UVLO
V
TMRH
V
TMRL
V
ACL
V
CB
5.8礎
230礎
58礎
58礎
5.8礎
5.8礎
INITIAL TIMING CYCLE
START-UP CYCLE
425112 F09
UV/0V
TIMER
GATE
SENSE